The subject application is related to subject matter disclosed in Japanese Patent Application No. H12-53674 filed on Feb. 29, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a processor, and especially, it relates to a semiconductor integrated circuit having a keeper circuit holding a signal indicative of a logical operation result.
2. Related Background Art
A node which is called a dynamic node whose logic dynamically changes in response to logic of an input signal exists inside a semiconductor integrated circuit. It is often the case that a keeper circuit is connected to this kind of node in order to avoid an unintentional change in the logic.
FIG. 1 is a circuit diagram showing a prior art keeper circuit and illustrates an example of constituting the keeper circuit by a PMOS transistor Q51. The keeper circuit shown in FIG. 1 is connected to input/output terminals of an inverter IV51, and an input of the inverter IV51 is maintained at a high level when an output of the inverter IV51 turns to a low level.
In the circuit shown in FIG. 1, however, since the PMOS transistor Q51 tries to maintain the high level when the input of the inverter IV51 is changed from the high level to the low level, and hence it disadvantageously takes time until the output logic of the inverter IV51 turns to the low level. Further, when the drive capability of the PMOS transistor Q51 is sufficiently large, the output logic of the inverter IV51 may not turn to the low level.
On the other hand, FIG. 2 is a circuit diagram showing a convention example in which a keeper circuit consisting of PMOS transistors Q52 and Q53 is connected to output terminals of NOR operation circuits 51 and 52, and this is a circuit diagram disclosed in FIG. 6 of Japanese Patent Application Laid-open No. 166216/1997. The PMOS transistors Q52 and Q53 shown in FIG. 2 are connected between input/output terminals of inverters IV52 and IV53. When the outputs of the inverters IV52 and IV53 turn to the low level, the PMOS transistors Q52 and Q53 are turned on to maintain inputs of the inverters IV52 and IV53 on the high level.
The circuit shown in FIG. 2 also has such a problem as that it takes a long time to change a logic of output signals from the inverters IV52 and IV53 when the logic of the input signal has varied, as similar to the circuit illustrated in FIG. 1. Furthermore, when the drive capability of the PMOS transistors Q52 and Q53 is too large, the logic of output signals from the inverters IV52 and IV53 may not change even if the logic of the input signal has varies.
On the other hand, FIG. 3 is a circuit diagram presented in ISSCC""98 (xe2x80x9cA 1.0 GHz Single-Issure 64 bit Power PC Integer Processorxe2x80x9d J. Silberman, et. al, IBM Austin Research Lab. ISSCC Session FP 15.1, Slide Supplement).
The circuit shown in FIG. 3 is different from the circuit of FIG. 2 in that a PMOS transistor Q54 and an NMOS transistor Q55 which are connected in series are newly provided at rear stages of NOR operation circuits 51 and 52 instead of the NAND gates G51 and G52.
The circuit shown in FIG. 3 is also provided with a keeper circuit consisting of the PMOS transistor Q52, and has the same problem as that of the circuit of FIG. 2.
On the other hand, FIG. 4 is a circuit diagram of a dual rail which outputs a result of an NOR operation and a result of an NAND operation carried out between two input signals. The circuit shown in FIG. 4 includes two NMOS transistors Q56 and Q57 which are connected to each other in parallel to execute the NOR operation, two NMOS transistors Q58 and Q59 which are connected to each other in series to execute the NAND operation, and PMOS transistors Q60 and Q61 which are connected to drain terminals of the transistors Q56 and Q57 and a drain terminal of the transistor Q58 and cross-multiplied to each other.
The PMOS transistors Q60 and Q61 acts as keeper circuits which prevent fluctuations in each drain voltage of the transistors Q56, Q57 and Q58.
In the circuit shown in FIG. 4, however, when the logic of an input signal is changed and each drain voltage of the transistors Q56, Q57 and Q58 is thereby about to vary, the PMOS transistors Q60 and Q61 operate so as to prevent the change of each drain voltage, and hence it disadvantageously takes time to change the logic of an output signal. Further, if the drive capability of the PMOS transistors Q60 and Q61 is high, the output logic may not change.
On the other hand, FIG. 5 is a circuit diagram showing a semiconductor integrated circuit having a latch load circuit 53 for holding a signal indicative of a result of the NOR operation and a signal indicative of a result of the NAND operation, these arithmetic operations being executed between two input signals.
The latch load circuit 53 shown in FIG. 5 includes transistors Q60 and Q62 connected in series between a power supply terminal and a drain terminal of the transistor Q57, transistors Q61 and Q63 connected in series between the power supply terminal and a drain terminal of the transistor Q58, and a transistor Q64 connected between source terminals of the transistors Q62 and Q63.
The transistors Q60 and Q61 are cross-multiplied to each other, and the transistors Q62 and Q63 are also cross-multiplied to each other.
The NOR operation result of the input signals is outputted from a connection point CN1 between the transistor Q60 and the transistor Q62, and the NAND operation result of the input signals is outputted from a connection point CN2 between the transistor Q61 and the transistor Q63. A transistor for pre-charge is connected to each of the connection points CN1 and CN2.
The latch load circuit 53 latches drain voltages of the transistors Q60 and Q62 and drain voltages of the transistors Q61 and Q63 by using an edge of a clock signal CLK. The semiconductor integrated circuit shown in FIG. 5 outputs differential signals each of which has the logic different from each other.
The semiconductor integrated circuit shown in FIG. 5, however, constantly outputs differential signals even if only one of the logic is utilized, which leads to a problem of increase in the circuit scale. Furthermore, when the semiconductor integrated circuit shown in FIG. 5 is used only when the differential signals are required, the application range is narrowed, thereby lowering the utility value.
In view of the above-described problems in the prior art, it is an object of the present invention to provide a semiconductor integrated circuit capable of stable operating at high speed.
To achieve this object, according to the present invention, there is provided a semiconductor integrated circuit having a logical operation function, comprising:
at least three of first logic operating means configured to output the results of different logic operations executed with respect to a plurality of input signals, any one of said at least three of first logic operating means outputting a signal having first logic in accordance with logic of said plurality of input signals; and
a plurality of keeper circuits which are provided respectively corresponding to said at least three of first logic operating means and can maintain an output voltage of said corresponding first logic operating means at a voltage in accordance with second logic,
wherein each of said plurality of keeper circuits forcibly sets an output from said corresponding logic arithmetic operating means to said second logic when an output from said first logic operating means other than said corresponding first logic operating means is said first logic.
According to the present invention, when the output logic of any first logic operating means changes, the corresponding keeper circuit operates so that the output logic of the first logic operating means varies, thereby increasing the logic change speed of the first logic operating means. Further, when an output from the first logic operating means other than the corresponding first logic operating means becomes the first logic, the keeper circuit forcibly sets the output from the corresponding first logic operating means to the second logic. As a result, fluctuations in the output logic of the semiconductor integrated circuit can be suppressed, thereby stabilizing the operation.
Additionally, according to the present invention, there is provided a semiconductor integrated circuit having a logical operation function, comprising:
at least two of first logic operating means configured to output the results of different logic operations executed with respect to a plurality of input signals, only one of said at least two of first logic operating means outputting a signal having first logic in accordance with logic of said plurality of input signals; and
a plurality of keeper circuits provided respectively corresponding to said at least two of first logic operating means,
xe2x80x83wherein each of said plurality of keeper circuits includes:
a first transistor capable of maintaining an output voltage of said corresponding first logic operating means at a voltage in accordance with second logic; and
second logic operating means configured to execute a predetermined logic operation by using output signals from said plurality of first logic operating means,
said first transistor being controlled to be turned on/off based on output logic of said second logic operating means.
Moreover, according to the present invention, there is provided a semiconductor integrated circuit having a logical operation function, comprising:
at least two of first logic operating means configured to output the results of different logic operations executed with respect to a plurality of input signals, only one of said at least two of first logic operating means outputting a signal having first logic in accordance with logic of said plurality of input signals; and
a plurality of keeper circuits provided respectively corresponding to said at least two of first logic operating means,
xe2x80x83wherein each of said plurality of keeper circuits includes:
a first transistor capable of maintaining an output voltage of said corresponding first logic operating means at a voltage in accordance with second logic;
a second transistor which is cross-multiplied with said first transistor and is capable of outputting a voltage in accordance with said second logic; and
a third transistor configured to output a voltage in accordance with an output from said first logic operating means other than said corresponding first logic operating means when output logic of said corresponding first logic operating means is said second logic,
said second transistor being turned on to output a voltage in accordance with said second logic when an output from said corresponding first logic operating means is said first logic,
said first transistor being turned on to maintain an output voltage of said corresponding first logic operating means at a voltage in accordance with said second logic when an output logic of said corresponding keeper circuit is said first logic.
In addition, according to the present invention, there is provided a semiconductor integrated circuit having a logical operation function, comprising:
at least two of first logic operating means configured to output results of different logic operations executed with respect to a plurality of input signals, at least one of said at least two of first logic operating means outputting a signal having first logic in accordance with logic of said plurality of input signals;
second logic operating means which are provided respectively corresponding to said at least two of first logic operating means and execute a predetermined logic operation by using output signals of said plurality of first logic operating means;
first and second transistors which are provided respectively corresponding to said at least two of first logic operating means and connected in series; and
pre-charging means capable of maintaining a voltage of a connection point of said first and second transistors at a predetermined voltage,
wherein said first and second transistors are controlled to be turned on/off based on an output from said second logic operating means,
said second logic operating means outputting a signal in accordance with an output of said first logic operating means other than said corresponding first logic operating means when said first transistor is turned on and outputting a signal in accordance with output logic of said corresponding first logic operating means when said first transistor is turned off.